The present invention relates generally to high speed digital data communication systems. In particular, the present invention relates to timing recovery solutions for use with such digital data communication systems.
Timing recovery is an important issue in many digital communication systems because the received signal must be sampled at an appropriate rate associated with the transmitter. In systems having no direct locking between the transmitter and receiver clocks, the receiver may be configured to track the transmitter clock, to monitor changes in the sampling rate, and to monitor changes in the sampling phase. Generally, timing recovery techniques seek to obtain an optimum receiver sampling rate along with an optimum receiver sampling phase.
Conventional timing recovery techniques for use with T-spaced receiver equalizers assume that the analyzed signal is free from interference such as echo or near end cross talk (NEXT). Practical high speed applications supporting 1,000,000 (or more) symbols per second cannot efficiently perform echo cancellation after equalization unless auxiliary echo cancellation procedures are implemented. Accordingly, it may be difficult to perform timing recovery based on the received signal in the presence of echo without further equalizing the signal used for the timing recovery analysis.
Because only one sample per symbol is taken in a T-spaced arrangement, timing recovery can be difficult to maintain. One prior art system utilizes a trial and error technique to find optimal sampling phase during the start up or initialization period. Such a trial and error timing recovery scheme may test several sampling phases to determine an optimum sampling phase for the current communication session. Although this may lead to acceptable immediate results, the repeated testing of sampling phases may require an unreasonable amount of time. Furthermore, such a technique cannot continuously monitor changes in line characteristics (e.g., as a result of temperature variations) during normal operation.
Other conventional timing recovery techniques can be interfered with during equalizer adaptation. Consequently, such prior art techniques cannot be effectively implemented in systems where the equalizers are periodically or continuously updated in accordance with variations in the channel characteristics.
In very high speed applications, conventional timing recovery methods based on digital signal processors may not be adequate because the processing speed may not be sufficiently fast. Accordingly, it would be desirable to implement a hardware model for a timing recovery technique compatible with high speed applications.
Accordingly, it is an advantage of the present invention that an improved timing recovery technique for a digital data communication system is provided.
Another advantage of the present invention is that it provides a timing recovery technique that is based on the impulse response of the receiver equalizer structure.
Another advantage is that the present invention provides a timing recovery technique that is suitable for use in a receiver having T-spaced equalizers.
A further advantage is that the timing recovery technique can be used in a receiver where echo cancellation is performed after equalization of the received signal.
Another advantage of the present invention is that it provides a timing recovery technique that can be effectively utilized throughout the normal operating mode of the digital data communication system and while the receiver equalizers are being updated.
A further advantage is that a timing recovery processing circuit according to the present invention can be implemented with high speed digital logic components in lieu of a digital signal processor.
The above and other advantages of the present invention may be carried out in one form by a timing recovery method for a high speed data communication device. The method obtains data indicative of a plurality of filter tap coefficients associated with an adaptive equalizer structure employed by the high speed data communication device, processes the data to quantify a cost function associated with an impulse response of the adaptive equalizer structure, and generates a sampling phase control signal. The sampling phase control signal is configured to adjust a sampling element associated with the high speed data communication device to thereby substantially optimize the cost function.